UPD9930 datasheet(21/80 Pages) RENESAS

21 / 80 page

µPD9930

D15 D14 D13 D12 D11 D10

SI input

Coding data (15 bits)

Sign bit

D15 D14 D13 D12 D11 D10

SO output

Coding data (13 bits)

Sign bit

Invalid data

2.1.8 DSP Interface

A clock synchronous serial I/O is built-in to exchange voice send/receive coding data with an external DSP.

16-bit data is transferred at 8 kHz by the serial clock (SCLK = 256 kHz), serial input (SI), serial output (SO),

and enable output (SEN) lines. The REQB is a terminal for allowing/inhibiting data transmission. There are

two modes for data input and output timing, and either can be selected by the DSPSEL terminal. Select the

mode matching the DSP serial interface input/output timing. Data format is as follows: Both SO output and SI

input are in 2's complement format with MSB first.

Figure 2-11 Data Format in DSP Interface

Remark A full code is output when the SO pin is +3.17 dBm0 (A/D 1.2 Vp-p).

Remark When a full code is input to the SI pin, the accessory output is 1.2 Vp-p.

Table 2-5 DSP Input/Output Timing Mode Selection

Pin input

DSPSEL

MODE1

MODE2

Table 2-6 Allowing Data Transmission

REQB pin Input

Data Transmission

Data transmission is allowed. Enable signal (SEN) is output at rising edge of FSYNC (8 kHz), and

data input/output is started.

Enable signal is not output and data are not input or output.

Mode

UPD9930 Datasheet(PDF) 21 Page - Renesas Technology Corp