HT48R02 datasheet(19/38 Pages) HOLTEK

19 / 38 page

HT48R01/HT48R02/HT48R03

Rev. 1.00

December 20, 2006

· Buzzer Function

PA0 and PA1 are pin-shared with the BZ and BZ

buzzer signals, respectively. If the Buzzer option is se-

lected, then if these pins are setup as outputs, the sig-

nals on PA0 (or PA1) will be the Buzzer signal. If setup

as inputs, they will always retain their original input

functions.

The buzzer output signals (in output mode) are con-

trolled by the PA0 data register only. The truth table for

PA0/BZ and PA1/BZ are listed below. Port A also has

a CMOS or Schmitt trigger input configuration option

(All port A I/O lines are controlled by a option bit).

The truth table for PA0/BZ and PA1/BZ is as shown.

PA0 I/O

IIII O O O OOOOO

PA1 I/O

I OOO I

I OOOOO

PA0 Mode

xxxx C B B C BBBB

PA1 Mode

x C B B x x x C C C B B

PA0 Data

x x 0 1 D 0 1 D0 0101

PA1 Data

x D xxxx x D1 DD x x

PA0 Pad Status IIII D 0 B D0 0B0B

PA1 Pad Status I D 0 B I

I D1 DD 0 B

Note: I: input; O: output; D, D0,D1: data;

B: buzzer option, BZ or BZ; x: don't care

C: CMOS output

Low Voltage Reset

- LVR

The microcontroller provides a low voltage reset circuit

in order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

0.9V~VLVR, such as when changing the battery, the LVR

will automatically reset the device internally.

The LVR includes the following specifications:

· The low voltage (0.9V~V

LVR) has to remain in this con-

dition for a time greater than 1ms. If the low voltage

state does not exceed 1ms, the LVR will ignore it and

will not perform a reset function.

· The LVR uses an

²OR² function with the external RES

signal to perform a chip reset.

The relationship between VDD and VLVR is shown below.

Note: VOPR is the voltage range for proper chip opera-

tion with a 4MHz system clock.

5 . 5 V

2 . 1 V

2 . 2 V

0 . 9 V

V D D

V O P R

V L V R

5 . 5 V

3 . 1 5 V

2 . 2 V

0 . 9 V

V D D

V O P R

V L V R

5 . 5 V

4 . 2 V

2 . 2 V

0 . 9 V

V D D

V O P R

V L V R

5 . 5 V

V D D

5 . 5 V

V L V R

0 . 9 V

0 V

R e s e t S i g n a l

R e s e t

* 1

* 2

N o r m a l O p e r a t i o n

R e s e t

L V R D e t e c t V o l t a g e

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilised, the SST provides an extra delay of

1024 system clock pulses before entering normal operation.

*2: Since the low voltage has to be maintained in its original state and exceed tLVR, therefore a tLVR delay enters

the reset mode.

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