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UPD77015 Datasheet(PDF) 21 Page - Renesas Technology Corp |
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UPD77015 Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 62 page  19 µPD77015, 77017, 77018 2.3.6 CJC: Condition Judge Circuit CJC judges whether condition is true or false with 40 bits input data. A conditional instruction is executed when the result is true, and not executed when the result is false. 2.4 Memory The µPD77017 has one instruction memory area (64K words × 32 bits) and two data memory areas (64K words × 16 bits each). It adopts Harvard-type architecture, with instruction memory area and data memory areas separated. The µPD77017 has 2 sets of data addressing units, which are dedicated for addressing data memory area. Each addressing unit consists of four data pointers, four index registers, a modulo register and addressing ALU. X memory area addresses are specified by DP0 to DP3, and Y memory area addresses are specified by DP4 to DP7. After memory access, DPn (with the same subscript), can be modified by DNn value. Modulo operation is performed with DMX for DP0 to DP3, with DMY for DP4 to DP7. |
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