TMS320VC549 datasheet(13/63 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

electrical characteristics over recommended operating case temperature range (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

High-level output voltage‡

VDD = 3.3"0.3 V, IOH = MAX

2.4

VOL

Low-level output voltage‡

IOL = MAX

0.4

IIZ

Input

current in

high

A[22:0]

VDD = MAXk

− 150

250

µA

IIZ

high

impedan

All other pins

VDD = MAX, VI = VSS to VDD

−10

µA

TRST

With internal pulldown

−10

800

Input

HPIENA

With internal pulldown, RS = 0

−10

400

Input

current

TMS, TCK, TDI, HPI||

With internal pullups

−400

current

(VI =VSS

to VDD)

D[15:0], HD[7:0]

Bus holders enabled, VDD = MAXk

−150

250

µA

(VI =VSS

to VDD)

X2/CLKIN

Oscillator enabled

−40

All other input-only pins

−10

IDDC

Supply current, core CPU

CVDD = 2.5 V, fx = 40 MHz,§ TC = 25°C

20¶

IDDP

Supply current, pins

DVDD = 3.3 V, fx = 40 MHz,§ TC = 25°C

12#

IDLE2

PLL

× 1 mode, 40 MHz input

IDD

Supply

current,

IDLE3

Divide-by-two mode, CLKIN stopped

(VC549-80 and VC549-100)

µA

IDD

current,

standby

IDLE3

Divide-by-two mode, CLKIN stopped

(VC549-120 only)

°C

Divide-by-two mode, CLKIN stopped

(VC549-120 only)

100

°C

Input capacitance

Output capacitance

† All values are typical unless otherwise specified.

‡ All input and output voltage levels except RS, INT0 −INT3, NMI, CNT, X2/CLKIN, CLKMD0 −CLKMD3 are LVTTL-compatible.

§ Clock mode: PLL × 1 with external source

¶ This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being

executed.

# This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,

refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).

|| HPI input signals except for HPIENA.

kVIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX)

TMS320VC549 Datasheet(PDF) 13 Page - Texas Instruments

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