TAS5036APFCRG4 datasheet(38/62 Pages) TI

38 / 62 page

System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes

SLES061B—November 2002—Revised January 2004

TAS5036A

< 2 ms

MCLK

RESET

ERR_RCVRY

ERR_RCVRY and MUTE can

be set at any time prior to 2 ms

following the LOW to HIGH

transition of RESET

MUTE

Wait a minimum of 100

µs

after the LOW to HIGH

transition of RESET

> 5 ms

Set serial interface format, data

rate, volume, ... via I2C

Release ERR_RCVRY and

then MUTE when I2C

registers are programmed

Volume ramp

up 120 ms

Figure 4−2. Extending the I2C Write Interval Following a Low-to-High Transition of the RESET Terminal

The operation of the TAS5036A can be tailored as desired to meet specific operating requirements by

adjusting the following:

•

Volume

•

Data sample rate

•

Emphasis/deemphasis settings

•

Individual channel mute

•

Automute delay register

•

DC-offset control registers

If desired, the TAS5036A can be set to perform an unmute sequence following the low-to-high transition of

the ERR_RCVRY terminal or the error recovery I2C command (register 0x03 bit D2). This capability is set by

writing 0x7F to the individual error recovery register (0x04) and 0x84 to the feature enable register (0x1F).

4.2

Data Sample Rate

If the master clock is well-behaved during the frequency transition (no MCLK_IN high or low clock periods less

than 20 ns) then a simple speed selection is performed by setting the DBSPD terminal or the serial control

to provide a completely silent transition. The timing of this control sequence is shown in Figure 4−3 and

Figure 4−4.

TAS5036APFCRG4 Datasheet(PDF) 38 Page - Texas Instruments

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