UPD754264 datasheet(39/69 Pages) RENESAS

39 / 69 page

µPD754264

Data Sheet U12487EJ1V2DS

(2) Legend in explanation of operation

A: A register, 4-bit accumulator

B: B register

C: C register

D: D register

E: E register

H: H register

L: L register

X: X register

: XA register pair; 8-bit accumulator

: BC register pair

: DE register pair

: HL register pair

XA’

: XA’ extended register pair

BC’

: BC’ extended register pair

DE’

: DE’ extended register pair

HL’

: HL’ extended register pair

: Program counter

: Stack pointer

: Carry flag, bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn

: Port n (n = 3, 6, 7, 8)

IME

: Interrupt master enable flag

IPS

: Interrupt priority selection register

×××

: Interrupt enable flag

RBS

: Register bank selection register

MBS

: Memory bank selection register

PCC

: Processor clock control register

.: Separation between address and bit

(

××): The contents addressed by ××

××H: Hexadecimal data

UPD754264 Datasheet(PDF) 39 Page - Renesas Technology Corp

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