RT8549L datasheet(21/24 Pages) RICHTEK

21 / 24 page

RT8549L

DS8549L-00 May 2019

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 4. Derating Curve of Maximum Power Dissipation

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

Layout Consideration

PCB layout is very important for designing switching power

converter circuits. The following layout guides should be

strictly followed for best performance of the RT8549L.



The power components, L1, D1, CIN1 and COUT must be

placed as close as possible to reduce power loop. The

PCB trace between power components must be as short

and wide as possible.



Place L1 and D1 as close as possible to LX pin. The

trace should be as short and wide as possible. Keep

the LX node away from the COMP, VDC, SMBDAT and

SMBCLK ground.



The compensation circuit (RCOMP, CCOMP) should be kept

away from the power loops and should be shielded with

a ground trace to prevent any noise coupling. Place the

compensation components as close as possible to the

COMP pin.



The exposed pad of the chip should be connected to a

large ground plane for thermal consideration.

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature TJ(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJA is the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125

°C. The junction-to-ambient thermal

resistance,

θJA, is highly package dependent. For a

WDFN-16L 5x5, the thermal resistance,

θJA, is 28.8°C/W

on a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at TA = 25

°C can be calculated as below :

PD(MAX) = (125

°C − 25°C) / (28.8°C/W) = 3.47W for a

WDFN-16L 5x5 package.

The maximum power dissipation depends on the operating

ambient temperature for the fixed TJ(MAX) and the thermal

resistance,

θJA. The derating curves in Figure 4 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

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