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HD74LS165AFPEL Datasheet(PDF) 4 Page - Renesas Technology Corp |
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HD74LS165AFPEL Datasheet(HTML) 4 Page - Renesas Technology Corp |
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4 / 8 page ![]() HD74LS165A Rev.3.00, Jul.15.2005, page 4 of 7 Testing Method Test Circuit 4.5V QH Load circuit 1 VCC RL CL Input P.G. Zout = 50 Ω Serial Input Shift/Load A B C D F G H Clock Clock Inhibit E QH Same as Load Circuit 1. Output Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveforms 1 Shift/ Load Serial Input Clock Inhibit 1.3V 1.3V 1.3V 1.3V 1.3V tsu tsu tsu 0V 0V 0V 3V 3V 3V Notes: A. The eight data inputs and the clock-inhibit input are low. Results are monitored at output QH at Tn + 7. B. The input pulse generators have the following characteristics: PRR < 1 MHz, duty cycle < 50%, Zout ≈ 50 Ω, t TLH ≤ 15 ns, t THL ≤ 6 ns. |
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