CS51313 datasheet(21/23 Pages) ONSEMI

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CS51313

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ρ = the copper resistivity (μΩ−mil);

L = length (mils);

W = width (mils);

t = thickness (mils).

For most PCBs the copper thickness, t, is 35 μm (1.37

mils) for one ounce copper; ρ = 717.86 μΩ−mil.

For a CPU load of 16 A the resistance needed to create a

50 mV drop at full load is:

RDROOP + 50 mV

IOUT

+ 50 mV

16 A +

3.1 mW

The resistivity of the copper will drift with the

temperature according to the following guidelines:

DR + 12% @ TA + +50°C;

DR + 34% @ TA + +100°C;

Droop Resistor Length, Width, and Thickness

The minimum width and thickness of the droop resistor

should primarily be determined on the basis of the

current−carrying capacity required, and the maximum

permissible droop resistor temperature rise. PCB

manufacturer design charts can be used in determining

current−carrying capacity and sizes of etched copper

conductors for various temperature rises above ambient.

For single conductor applications, such as the use of the

droop resistor, PCB design charts show that for a droop

resistor with a required current−carrying capacity of 16 A,

and a 45°C temperature rise above ambient, the

recommended cross section is 275 mil2.

t + 275 mil2

where:

W = droop resistor width;

t = droop resistor thickness.

For 1 oz. copper, t = 1.37 mils, therefore W = 201 mils =

0.201 in.

R + ò

where:

R = droop resistor value;

ρ = 0.71786 mΩ−mil (1 oz. copper);

L = droop resistor length;

W = droop resistor width.

RDROOP + 3.3 mW

3.3 mW + 0.71786 mW−mil

201 mils

1.37 mils

Hence, L = 1265 mils = 1.265 in.

In layouts where it is impractical to lay out a droop resistor

in a straight line 1265 mils long, the embedded PCB trace

can be “snaked” to fit within the available space.

THERMAL MANAGEMENT

Thermal Considerations for Power MOSFETs

In order to maintain good reliability, the junction

temperature of the semiconductor components should be

kept to a maximum of 150°C or lower. The thermal

impedance (junction to ambient) required to meet this

requirement can be calculated as follows:

Thermal Impedance +

TJ(MAX) * TA

Power

A heatsink may be added to TO−220 components to

reduce their thermal impedance. A number of PC board

layout techniques such as thermal vias and additional copper

foil area can be used to improve the power handling

capability of surface mount components.

EMI MANAGEMENT

As a consequence of large currents being turned on and off

at high frequency, switching regulators generate noise as a

consequence of their normal operation. When designing for

compliance with EMI/EMC regulations, additional

components may be added to reduce noise emissions. These

components are not required for regulator operation and

experimental results may allow them to be eliminated. The

input filter inductor may not be required because bulk filter

and bypass capacitors, as well as other loads located on the

board will tend to reduce regulator di/dt effects on the circuit

board and input power supply. Placement of the power

component to minimize routing distance will also help to

reduce emissions.

LAYOUT GUIDELINES

When laying out the CPU buck regulator on a printed

circuit board, the following checklist should be used to

ensure proper operation of the CS51313.

1.Rapid changes in voltage across parasitic capacitors and

abrupt changes in current in parasitic inductors are

major concerns for a good layout.

2.Keep high currents out of sensitive ground connections.

3.Avoid ground loops as they pick up noise. Use star or

single point grounding.

4.For high power buck regulators on double−sided PCBs

a single ground plane (usually the bottom) is

recommended.

5.Even though double sided PCBs are usually sufficient

for a good layout, four−layer PCBs are the optimum

approach to reducing susceptibility to noise. Use the

two internal layers as the power and GND planes, the

top layer for power connections and component vias,

and the bottom layer for the noise sensitive traces.

6.Keep the inductor switching node small by placing the

output inductor, switching and synchronous FETs

close together.

7.The MOSFET gate traces to the IC must be as short,

straight, and wide as possible.

8.Use fewer, but larger output capacitors, keep the

capacitors clustered, and use multiple layer traces

with heavy copper to keep the parasitic resistance

low.

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