ZSPM1035C / ZSPM1035D Datasheet

© 2016 Integrated Device Technology, Inc.

13

January 25, 2016

2.3.

Available Packages

The ZSPM1035C/D is available in a 24-pin QFN package. The pin-out is shown in Figure 2.3. The mechanical

drawing of the package can be found in Figure 5.1.

Figure 2.3

Pin-Out QFN24 Package

3

Functional Description

3.1.

Power Supply Circuitry, Reference Decoupling, and Grounding

The ZSPM1035C/D incorporates several internal power regulators in order to derive all required supply and bias

voltages from a single external supply voltage. This supply voltage can be either 5V or 3.3V depending on

whether the internal 3.3V regulator should be used. If the internal 3.3V regulator is not used, 3.3V must be

supplied to the 3.3V and 5V supply pins. Decoupling capacitors are required at the VDD33, VDD18, and AVDD18

pins (1.0µF minimum; 4.7µF recommended). If the 5.0V supply voltage is used, i.e., the internal 3.3V regulator is

used, a small load current can be drawn from the VDD33 pin. This can be used to supply pull-up resistors for

example.

The reference voltages required for the analog-to-digital converters are generated within the ZSPM1035C/D.

External decoupling must be provided between the VREFP and ADCVREF pins. Therefore, a 4.7µF capacitor is

required at the VREFP pin, and a 100nF capacitor is required at the ADCVREF pin. The two pins should be

connected with approximately 50

Ω resistance in order to provide sufficient decoupling between the pins.

Three different ground connections (the pad, AGND pin, and GND pin) are available on the outside of the

package. These should be connected together to a single ground tie. A differentiation between analog and digital

ground is not required.

PAD

19

20

21

22

24 23

ISNSP

ISNSN

VFBP

VFBN

AGND

4

2

1

3

5

6

VREFP

7

8

12

10

9

11

CONTROL

PGOOD

GPIO1

GPIO2

GPIO3

13

14

15

16

18

17

GPIO0