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TMS320C32PCMA50 Datasheet(PDF) 31 Page - Texas Instruments

Part # TMS320C32PCMA50
Description  DIGITAL SIGNAL PROCESSOR
PDF  45 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320C32PCMA50 Datasheet(HTML) 31 Page - Texas Instruments

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TMS320C32
DIGITAL SIGNAL PROCESSOR
SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996
31
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
timing for RESET [Q = tc(CI)] (see Figure 26)
NO
’C32 - 40
’C32 - 50
’C32 - 60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
50
tsu(RESET)
Setup time, RESET before CLKIN low
10
Q†
10
Q†
7
Q†
ns
51
td(CLKINH-H1H)
Delay time, CLKIN high to H1 high
2
12
2
10
2
10
ns
52
td(CLKINH-H1L)
Delay time, CLKIN high to H1 low
2
12
2
10
2
10
ns
53
tsu(RESETH-H1L)
Setup time, RESET high before H1 low and
after ten H1 clock cycles
9
7
6
ns
54
td(CLKINH-H3L)
Delay time, CLKIN high to H3 low
2
12
2
10
2
10
ns
55
td(CLKINH-H3H)
Delay time, CLKIN high to H3 high
2
12
2
10
2
10
ns
56
tdis(H1H-D)
Disable time, H1 low to D in the
high-impedance state
13‡
12‡
11‡
ns
57
tdis(H3HL-A)
Disable time, H3 low to A in the
high-impedance state
9‡
8‡
7‡
ns
58.1
td(H3H-CONTROLH)
Delay time, H3 high to control signals high
9‡
8‡
7‡
ns
58.2
td(H1H-RWH)
Delay time, H1 low to R / W high
9‡
8‡
7‡
ns
59
td(H1H-IACKH)
Delay time, H1 high to IACK high
9‡
8‡
7‡
ns
60
tdis(RESETL-ASYNCH)
Disable time, RESET low to asynchronous
reset signals in the high-impedance state
21‡
17‡
14‡
ns
† Assured by design but not tested
‡ Assured from characterization but not tested



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