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ES9018S Datasheet(PDF) 34 Page - ESS Technology,Inc |
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ES9018S Datasheet(HTML) 34 Page - ESS Technology,Inc |
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34 / 54 page ![]() 2.3 ES9018S Product Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 34 Register 45-42: STAGE 2 FIR COEFFICIENTS Bits [31:0] Default - Bits Mnemonic Description [31:0] STAGE2_FIR_COEFFICIENTS These 32 bits are used for writing the stage 1 FIR coefficients. See the programming section for more information. Register 71-48: SPDIF CHANNEL STATUS DATA Bits [191: 0] Default - Bits Mnemonic Description [191: 0] SPDIF_CHANNEL_STATUS_DATA These registers allow read back of the SPDIF channel status. The status definition is different for the customer configuration (Table 7) and professional configuration (Table 8) |
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