SST25VF040B_V01 datasheet(15/31 Pages) MICROCHIP

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DS20005051F-page 15

SST25VF040B

5.12

Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write

Enable-Latch bit and AAI bit to ‘0’ disabling any new

Write operations from occurring. The WRDI instruction

will not terminate any programming operation in prog-

ress. Any program operation in progress may continue

up to TBP after executing the WRDI instruction. CE#

must be driven high before the WRDI instruction is exe-

cuted.

FIGURE 5-14:

WRITE DISABLE (WRDI)

SEQUENCE

5.13

Enable Write STATUS Register

(EWSR)

The Enable Write STATUS Register (EWSR) instruction

arms the Write STATUS Register (WRSR) instruction

and opens the STATUS register for alteration. The

Write STATUS Register instruction must be executed

immediately after the execution of the Enable Write

STATUS Register instruction.

This two-step instruction sequence of the EWSR instruc-

tion followed by the WRSR instruction works like SDP

(software data protection) command structure which

prevents any accidental alteration of the STATUS reg-

ister values. CE# must be driven low before the EWSR

instruction is entered and must be driven high before

the EWSR instruction is executed.

5.14

Write STATUS Register (WRSR)

The Write STATUS Register instruction writes new val-

ues to the BP3, BP2, BP1, BP0, and BPL bits of the

STATUS register. CE# must be driven low before the

command sequence of the WRSR instruction is entered

and driven high before the WRSR instruction is exe-

cuted. See Figure 5-15 for EWSR or WREN and WRSR

instruction sequences.

Executing the Write STATUS Register instruction will

be ignored when WP# is low and BPL bit is set to ‘1’.

When the WP# is low, the BPL bit can only be set from

‘0’ to ‘1’ to lock-down the STATUS register, but cannot

be reset from ‘1’ to ‘0’. When WP# is high, the lock-

down function of the BPL bit is disabled and the BPL,

BP0, and BP1 and BP2 bits in the STATUS register can

all be changed. As long as BPL bit is set to ‘0’ or WP#

pin is driven high (VIH) prior to the low-to-high transition

of the CE# pin at the end of the WRSR instruction, the

bits in the STATUS register can all be altered by the

WRSR instruction. In this case, a single WRSR instruction

can set the BPL bit to ‘1’ to lock down the STATUS reg-

ister as well as altering the BP0, BP1, and BP2 bits at

the same time. See Table 4-1 for a summary descrip-

tion of WP# and BPL functions.

FIGURE 5-15:

ENABLE WRITE STATUS REGISTER (EWSR) OR WRITE ENABLE (WREN) AND

WRITE STATUS REGISTER (WRSR) SEQUENCE

CE#

SCK

0 1 234 5 6 7

MODE 0

MODE 3

High-Impedance

MODE 0

STATUS

7 6 5 4321 0

MODE 3

SCK

CE#

MODE 0

50 or 06

0 1 234 5 6 7

0 1 234 5 6 789 10 11 12 13 14 15

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