CAT25C64LSATE13 datasheet(7/11 Pages) CATALYST

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CAT25C32/64

Doc. No. 1001, Rev. G

READ Sequence

The part is selected by pulling

CS low. The 8-bit read

instruction is transmitted to the CAT25C32/64, fol-

lowed by the 16-bit address(the three Most Significant

Bits are don’t care for 25C64 and four most significant

bits are don't care for 25C32).

After the correct read instruction and address are sent,

the data stored in the memory at the selected address

is shifted out on the SO pin. The data stored in the

memory at the next address can be read sequentially

by continuing to provide clock pulses. The internal

address pointer is automatically incremented to the

next higher address after each byte of data is shifted

out. When the highest address (1FFFh for 25C64 and

FFFh for 25C32) is reached, the address counter rolls

over to 0000h allowing the read cycle to be continued

indefinitely. The readoperation is terminated by pulling

the

CS high.

To read the status register, RDSR instruction should be

sent. The contents of the status register are shifted out on

the SO line. The status register may be read at any time

even during a write cycle. Read sequece is illustrated in

Figure 4. Reading status register is illustrated in Figure 5.

WRITE Sequence

The CAT25C32/64 powers up in a Write Disable state. Prior

to any write instructions, the WREN instruction must be

sent to CAT25C32/64. The device goes into Write enable

state by pulling the

CS low and then clocking the WREN

instruction into CAT25C32/64. The

CS must be brought

high after the WREN instruction to enable writes to the

device. If the write operation is initiated immediately after

the WREN instruction without

CS being brought high, the

data will not be written to thearray because the write enable

latch will not have been properly set. Also, for a successful

write operation the address of the memory location(s) to be

programmed must be outside the protected address field

location selected by the block protection level.

Figure 4. Read Instruction Timing

Figure 5. RDSR Instruction Timing

Note: Dashed Line= mode (1, 1) — — — —

0000001

BYTE ADDRESS*

0123456789

*Please check the instruction set table for address

OPCODE

DATA OUT

MSB

HIGH IMPEDANCE

345

911

SCK

DATA OUT

MSB

HIGH IMPEDANCE

OPCODE

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