WM8728

Production Data

w

PD Rev 4.2 April 2004

11

MPU 2-WIRE INTERFACE TIMING

Figure 5 Program Register Input Timing - 2-Wire Serial Control Mode

Test Conditions

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Program Register Input Information

SCK pulse cycle time

80

ns

SCK pulse width low

20

ns

SCK pulse width high

20

ns

SDIDEM to SCK data set-up

time for start signal

10

ns

SDIDEM from SCK data hold

time for start signal

10

ns

SDIDEM to SCK data set-up

time

20

ns

SCK to SDIDEM data hold time

20

ns

SCK rise time

5

ns

SCK fall time

5

ns

SDIDEM rise time

5

ns

SDIDEM fall time

5

ns

SDIDEM to SCK data set-up

time for stop signal

10

ns

Notes:

1.

The address for the device in the 2-wire mode is 001101X (binary) with the last bit selectable.

2.

In the two-wire interface mode, the CSBIWL pin indicates the final bit of the chip address.

3.

In 2-wire mode the LATI2S pin should be tied to either DGND or DVSS to avoid noise toggling the interface into 3-wire

mode.