WM8777 datasheet(39/103 Pages) WOLFSON

39 / 103 page

Pre-Production

WM8777

PP Rev 3.0 January 2005

BIT

LABEL

DEFAULT

DESCRIPTION

(18h)

Primary

Interface Control (RX)

5:4

PAIFRX_WL[1:0]

(1Bh)

Primary Interface

Control (TX)

5:4

PAIFTX_WL [1:0]

(3Eh)

Secondary Interface

Control

5:4

SAIF_WL [1:0]

Input Word Length

00 = 16 bit data

01 = 20 bit data

10 = 24 bit data

11 = 32 bit data

Table 28 Word Length Registers

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programmed to receive 16 or 20 bit data, the WM8777 pads the unused LSBs with zeros. If

the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

Note: In 24 bit I²S mode, any width of 24 bits or less is supported provided that LRCLK is high for a

minimum of 24 PBCLKs and low for a minimum of 24 PBCLKs. If exactly 32 bit clocks occur in one

left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.

POWERDOWN MODES

The WM8777 has powerdown control bits allowing specific parts of the WM8777 to be powered down

when not in use. The 6-channel input source selector and input buffer may be powered down using

control bit AINPD. When AINPD is set all inputs to the source selector (AIN1L/R to AIN6L/R) are

switched to a buffered VMIDADC and the ADC is also powered off. The control bit ADCPO powers

off the ADC.

The four stereo DACs each have a separate powerdown control bit, DACPD[3:0] allowing individual

stereo DACs to be powered down when not in use. The analogue output mixers and PGAs may also

be powered down by setting OUTPD1/2/3/4. OUTPD1/2/3/4 also switch the analogue outputs

VOUTL/R to VMIDDAC to maintain a dc level on the output. SPDIFTXD and SPDIFRXD will

powerdown the S/PDIF transmitter and receiver.

Setting all of AINPD, ADCPD, DACPD[3:0], SPDIFTXD, SPDIFRXD and OUTPD[3:0] will powerdown

everything except the references VMIDADC, ADCREF and VMIDDAC. These may be powered down

by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended

that the 6-channel input mux and buffer, ADC, DAC and output mixers and PGAs are powered down

before setting PDWN. The default is for all powerdown bits to be set except PDWN.

BIT

LABEL

DEFAULT

DESCRIPTION

PWDN

Chip Powerdown Control (works

in tandem with the other

powerdown registers):

0 = All digital circuits running,

outputs are active

1 = All digital circuits in power

save mode, outputs muted

ADCPD

ADC powerdown:

0 = ADC enabled

1 = ADC disabled

5:2

DACPD[3:0]

1111

DAC powerdowns (0 = DAC

enabled, 1 = DAC disabled)

DACPD[0] = DAC1

DACPD[1] = DAC2

DACPD[2] = DAC3

DACPD[3] = DAC4

SPDIFTXD

SPDIF_TX powerdown

0 = SPDIF_TX enabled

1 = SPDIF_TX disabled

(1Ah)

Powerdown Control

SPDIFRXD

SPDIF_RX powerdown

0 = SPDIF_RX enabled

1 = SPDIF_RX disabled

WM8777 Datasheet(PDF) 39 Page - Wolfson Microelectronics plc

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