WM8955LSEFLSLASHR datasheet(31/46 Pages) WOLFSON

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Production Data

WM8955L

PD Rev 4.2 March 2006

MASTER CLOCK AND PHASE LOCKED LOOP

The WM8955L has an on-chip phase-locked loop (PLL) circuit that can be used to:

•

generate a master clock for the WM9755L audio function from another external clock,

e.g. in telecoms applications.

•

generate a clock for another part of the system from an existing audio master clock.

The PLL circuit is shown below.

DIGITAL

CORE

MCLK

f/2

PLL

R = f

2 / f1

CLKOUT

f/2

MCLK

SEL

CLKOUT

SEL

MCLK

DIV2

CLKOUT

DIV2

f/4

f/2

PLLOUT

DIV2

CLKOUTEN

Figure 19 PLL Circuit

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKOUTDIV2

CLKOUT Divide by 2

0: Divide disabled

1: Divide enabled

R8 (08h)

Sample Rates

MCLKDIV2

MCLK Divide by 2

0: Divide disabled

1: Divide enabled

MCLKSEL

Select internal master clock

0: from MCLK pin

1: from PLL (make sure PLLEN=1)

CLKOUTEN

CLKOUT Enable

0: Pin disabled (tri-state)

1: Pin Enabled

CLKOUTSEL

Select source of CLKOUT

0: from MCLK pin

1: from PLL (make sure PLLEN=1)

PLLOUTDIV2

PLL Output Divide by 2

0: Divide disabled

1: Divide enabled

PLL_RB

0: PLL held in reset

1: PLL running (if PLLEN=1)

R43 (2Bh)

Clocking and

PLL

PLLEN

PLL Enable

0: PLL disabled; 1: PLL enabled.

Table 21 PLL and Clocking Control

WM8955LSEFL/R Datasheet(PDF) 31 Page - Wolfson Microelectronics plc

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