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AT83SND2CMP3B Datasheet(PDF) 233 Page - ATMEL Corporation |
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AT83SND2CMP3B Datasheet(HTML) 233 Page - ATMEL Corporation |
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233 / 241 page  233 4341F–MP3–03/06 AT8xC51SND2C/MP3B 24.4.5.3 Waveforms Figure 24-28. External Clock Waveform Figure 24-29. AC Testing Input/Output Waveforms Note: 1. During AC testing, all inputs are driven at V DD -0.5 V for a logic 1 and 0.45 V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 24-30. Float Waveforms Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH= ±20 mA. 0.45 V T CLCL VDD - 0.5 VIH1 VIL TCHCX TCLCH T CHCL T CLCX 0.45 V V DD - 0.5 0.7 VDD 0.3 VDD VIH min VIL max INPUTS OUTPUTS V LOAD VOH - 0.1 V VOL + 0.1 V VLOAD + 0.1 V VLOAD - 0.1 V Timing Reference Points |
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