O V ERVI EW

®

Phone: 949-450-8700

Fax: 949-450-8710

E-mail: info@broadcom.com

Web: www.broadcom.com

BROADCOM CORPORATION

16215 Alton Parkway, P.O. Box 57013

Irvine, California 92619-7013

© 2006 by BROADCOM CORPORATION. All rights reserved.

8021-PB04-R

04/14/06

the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries

and/or the EU. Any other trademarks or trade names mentioned are the property of their respective

owners.

BCM8021 Block Diagram

The BCM8021 device integrates XAUI serializer/deserializer (SerDes)

channels leveraging Broadcom’s high-performance mixed-signal design

experience along with advanced 0.13µ CMOS process technology. This,

combined this with a robust architecture offering the highest degree of

flexibility, results is a highly programmable, lowest power SerDes

solution for network line-card and backplane applications.

An internal MUX connects the parallel and serial ports to enable fully

redundant operation. The MUX enables an active serial link to be

switched to the parallel interface, while a protection serial link can be

continuously monitored to insure its condition. If the active link fails, the

protection link can be muxed over through external control to the parallel

interface.

On the parallel side of the device, transmitters and receivers interface

with a 32-bit wide data (XGMII) along with the clock and control

signals. The low-speed I/O supports HSTL (1.5V or 1.8V) or SSTL_2

(2.5V) interfaces.

On the serial side of the device, transmitters and receivers support XAUI

serial transmission rates. An on-chip phase lock loop (PLL) synthesizes

the supplied reference clock to support the desired transmit rate, while

vlock and data recovery (CDR) units recover the receive rate clock for

timing.

For high-speed serial copper connections, the device incorporates both

transmit pre-emphasis on the transmit channels and receive equalization

on the receive channels. Transmit pre-emphasis is programmable to

improve the overall cable reach and compensate for electrical

imperfections associated with traces and connectors. Receive

equalization provides optimal performance over a variety of receive

interfaces.

Highly programmable test capabilities exist within the device to support

high-speed and low-speed loopback using generators/checkers that

support PRBS 27 to 231 patterns along with IEEE802.3ae-defined test

patterns. A complete evaluation kit, including an evaluation board,

related software, and documentation is available upon request.