6

AT24C01A/02/04/08/16

3256F–SEEPR–10/04

STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode

which is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the

completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-

wire part can be reset by following these steps:

1.

Clock up to 9 cycles.

2.

Look for SDA high in each cycle while SCL is high.

3.

Create a start condition.

Bus Timing

Figure 2. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

Note:

1. The write cycle time t

twr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA