AT89C51AC2 datasheet(25/121 Pages) ATMEL

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A/T89C51AC2

4127G–8051–05/06

External Space

Memory Interface

The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD, WR, and ALE).

Figure 13 shows the structure of the external address bus. P0 carries address A7:0

while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17

describes the external memory interface signals.

Figure 13. External Data Memory Interface Structure

Table 17. External Data Memory Interface Signals

External Bus Cycles

This section describes the bus cycles the A/T89C51AC2 executes to read (see

Figure 14), and write data (see Figure 15) in the external data memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-

mation on X2 mode.

Slow peripherals can be accessed by stretching the read and write cycles. This is done

using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR

signals from 3 to 15 CPU clock periods.

For simplicity, the accompanying figures depict the bus cycle waveforms in idealized

form and do not provide precise timing information. For bus cycle timing parameters

refer to the Section “AC Characteristics”.

Signal

Name

Type

Description

Alternative

Function

A15:8

Address Lines

Upper address lines for the external bus.

P2.7:0

AD7:0

I/O

Address/Data Lines

Multiplexed lower address lines and data for the external

memory.

P0.7:0

ALE

Address Latch Enable

ALE signals indicates that valid address information are available

on lines AD7:0.

Read

Read signal output to external data memory.

P3.7

Write

Write signal output to external memory.

P3.6

RAM

PERIPHERAL

A/T89C51AC2

AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

Latch

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