UJA1069 datasheet(56/64 Pages) PHILIPS

56 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

56 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125

°C ambient

temperature on wafer level (pretesting). Cased products are 100 % tested at 25

°C ambient temperature (ﬁnal testing). Both pretesting

and ﬁnal testing use correlated test conditions to cover the speciﬁed temperature and power supply voltage range.

[2]

SPI timing is guaranteed for VBAT42 voltages down to 5 V. For VBAT42 voltages down to 4.5 V the guaranteed SPI timing values double, so

at these lower voltages a lower maximum SPI communication speed must be observed.

[3]

tbit = selected bit time, depends on LSC bit; 50 µs or 96 µs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R1/R2/C1):

Ω/1 kΩ/10 nF; 1 kΩ/2 kΩ/6.8 nF; 1 kΩ/open/1 nF; see Figure 25 and Figure 26.

[4]

[5]

Interrupt output; pin INTN

tINTN

interrupt release

after SPI has read out the

Interrupt register

µs

Oscillator

fosc

oscillator frequency

460.8

512

563.2

kHz

Table 26.

Dynamic characteristics …continued

Tvj = −40 °C to +150 °C; VBAT42 =5.5 V to52V; VBAT14 =5.5 V to27V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

δ1 δ3

bus rec

() min

()

bit

-------------------------------

δ2 δ4

bus rec

() max

()

bit

--------------------------------

Fig 24. SPI timing

001aaa405

SCS

SCK

SDI

SDO

MSB

LSB

MSB

LSB

tDOV

floating

tsu

tSCKL

tSCKH

tlead

Tcyc

tlag

tSSH

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