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EFM32GG11 Datasheet(PDF) 97 Page - Silicon Laboratories

Part # EFM32GG11
Description  EFM32 Giant Gecko Series 1 Family EFM32GG11 Family Data Sheet
PDF  261 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EFM32GG11 Datasheet(HTML) 97 Page - Silicon Laboratories

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SDIO MMC SDR Mode Timing at 1.8 V
Timing is specified at 1.62 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVES-
TRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF, between 10 and 20 pF, or be-
tween 20 and 30 pF on all pins.
Table 4.56. SDIO MMC SDR Mode Timing (Location 0, 1.62 V I/O)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
26
MHz
Using HFXO
—
—
26
MHz
Clock low time
tWL
Using HFRCO, AUXHFRCO, or
USHFRCO
17.3
—
—
ns
Using HFXO
14.9
—
—
ns
Clock high time
tWH
Using HFRCO, AUXHFRCO, or
USHFRCO
17.3
—
—
ns
Using HFXO
14.9
—
—
ns
Clock rise time
tR
1.1
—
6.6
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
5.1
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
Output delay time, SD_CLK
to CMD, DAT[0:7] valid
tODLY
—
—
17.7
ns
Output hold time, SD_CLK to
CMD, DAT[0:7] change
tOH
3
—
—
ns
Table 4.57. SDIO MMC SDR Mode Timing (Location 1, 1.62 V I/O)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Clock frequency during data
transfer
FSD_CLK
Using HFRCO, AUXHFRCO, or
USHFRCO
—
—
23
MHz
Using HFXO
—
—
23
MHz
Clock low time
tWL
Using HFRCO, AUXHFRCO, or
USHFRCO
19.6
—
—
ns
Using HFXO
16.9
—
—
ns
Clock high time
tWH
Using HFRCO, AUXHFRCO, or
USHFRCO
19.6
—
—
ns
Using HFXO
16.9
—
—
ns
Clock rise time
tR
1.1
—
6.6
ns
Input setup time, CMD,
DAT[0:7] valid to SD_CLK
tISU
6.1
—
—
ns
Input hold time, SD_CLK to
CMD, DAT[0:7] change
tIH
2.5
—
—
ns
EFM32GG11 Family Data Sheet
Electrical Specifications
silabs.com | Building a more connected world.
Rev. 1.2 | 97



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