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ISP1161 Datasheet(PDF) 21 Page - NXP Semiconductors |
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ISP1161 Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 127 page  Philips Semiconductors ISP1161 Full-speed USB single-chip host and device controller Product data Rev. 01 — 3 July 2001 21 of 130 9397 750 08313 © Philips Electronics N.V. 2001. All rights reserved. Bits RESET, RESUME, EOT and SOF are cleared upon reading the Interrupt Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated Endpoint Status Register. Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the current bus status when reading the Interrupt Register. SETUP and OUT token interrupts are generated after ISP1161’s DC has acknowledged the associated data packet. In bulk transfer mode, the ISP1161’s DC will issue interrupts for every ACK received for an OUT token or transmitted for an IN token. In isochronous mode, an interrupt is issued upon each packet transaction. The firmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt Enable Register. If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows the firmware to keep data transfer synchronized with the host. After 3 missed SOF events the ISP1161’s DC will enter ‘suspend’ state. An alternative way of handling isochronous data transfer is to enable both the SOF and the PSOF interrupts and disable the interrupt for each isochronous endpoint. Fig 22. DC interrupt logic. MGT946 RESET SUSPND RESUME SOF EP14 ... EP0IN .. . .. . .. . .. . EP0OUT EOT IERST DC Interrupt register DC Interrupt Enable register IESUSP IERESM IESOF IEP14 ... IEP0IN IEP0OUT IEEOT DC Device Mode register INTENA INTLVL DC Hardware Configuration register INTPOL PULSE GENERATOR INT2 1 0 |
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