M41000002M datasheet(17/66 Pages) AMD

17 / 66 page

Am41DL32x8G

September 5, 2002

PR ELI M I NARY

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE#f and RESET# pins are both held at V

CC ± 0.3 V.

(Note that this is a more restricted voltage range than

IH.) If CE#f and RESET# are held at VIH, but not

within V

CC ± 0.3 V, the device will be in the standby

mode, but the standby current will be greater. The de-

vice requires standard access time (t

CE) for read

access when the device is in either of these standby

modes, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

CC3 in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#f, WE#, and OE# control signals. Standard ad-

dres s ac c e s s ti mi ngs pr ov ide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

CC4 in the DC Characteristics table represents the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the

RESET# pin is driven low for at least a period of t

RP,

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V

SS ± 0.3 V, the de-

vice draws CMOS standby current (I

CC4). If RESET# is

held at V

IL but not within VSS ± 0.3 V, the standby cur-

rent will be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t

READY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not ex-

ecuting (RY/BY# pin is “1”), the reset operation is

completed within a time of t

READY (not during Embed-

ded Algorithms). The system can read data t

RH after

the RESET# pin returns to V

IH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at V

IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 5.

Device Bank Division

Device

Part Number

Bank 1

Bank 2

Megabits

Sector Sizes

Megabits

Sector Sizes

Am29DL322G

4 Mbit

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

28 Mbit

Fifty-six

64 Kbyte/32 Kword

Am29DL323G

8 Mbit

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

24 Mbit

Forty-eight

64 Kbyte/32 Kword

Am29DL324G

16 Mbit

Eight 8 Kbyte/4 Kword,

thirty-one 64 Kbyte/32 Kword

16 Mbit

Thirty-two

64 Kbyte/32 Kword

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