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M41000002P Datasheet(PDF) 57 Page - Advanced Micro Devices |
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M41000002P Datasheet(HTML) 57 Page - Advanced Micro Devices |
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57 / 66 page ![]() 56 Am41DL32x8G September 5, 2002 PR ELI M I NARY AC CHARACTERISTICS SRAM Read Cycle Note: CE1#s = OE# = V IL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 28. SRAM Read Cycle—Address Controlled Parameter Symbol Description Speed Options Unit 70 85 tRC Read Cycle Time Min 70 85 ns t AA Address Access Time Max 70 85 ns tCO1, tCO2 Chip Enable to Output Max 70 85 ns t OE Output Enable Access Time Max 35 45 ns tBA LB#s, UB#s to Access Time Max 70 85 ns tLZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min 10 ns t BLZ UB#, LB# Enable to Low-Z Output Min 10 ns t OLZ Output Enable to Low-Z Output Min 5 ns t HZ1, tHZ2 Chip Disable to High-Z Output Max 25 ns t BHZ UB#s, LB#s Disable to High-Z Output Max 25 ns t OHZ Output Disable to High-Z Output Max 25 ns t OH Output Data Hold from Address Change Min 10 ns ddress ata Out Previous Data Valid Data Valid tAA tRC tOH |
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