AM29PDL128G datasheet(37/71 Pages) AMD

37 / 71 page

Am29PDL128G

October 28, 2004

P R E L IM IN A R Y

cess the SecSi Sector region by issuing the three-cy-

cle Enter SecSi Sector command sequence. The

device continues to access the SecSi Sector region

until the system issues the four-cycle Exit SecSi Sec-

tor command sequence. The Exit SecSi Sector com-

mand s equ enc e ret u r n s the dev ic e to nor m a l

operation. The SecSi Sector is not accessible when

the device is executing an Embedded Program or em-

bedded Erase algorithm. Table 15 and Table 17 show

the address and data requirements for both command

sequences. See also “SecSi™ (Secured Silicon) Sector

Flash Memory Region” for further information.

Note:

The ACC function and unlock bypass modes are not

available when the SecSi Sector is enabled.

Double Word/Word Program Command

Sequence

The system may program the device by double word

or word, depending on the state of the WORD# pin.

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is

not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 14 and Table 16 show

the address and data requirements for the program

command sequence.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

on page 46 for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note: A hard-

ware reset immediately terminates the program

operation.

Note: the SecSi Sector, autoselect, and CFI

functions are unavailable when a [program/erase] op-

eration is in progress. The program command se-

quence should be reinitiated once that bank has

returned to the read mode, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read shows that the data is

still “0.” Only erase operations convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram data to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. That bank

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 14 and Table 16 show the require-

ments for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. (See Table 14).

The device offers accelerated program operations

through the ACC pin. When the system asserts V

HH on

the ACC pin, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the higher voltage on the

ACC pin to accelerate the operation.

Note: The ACC

pin must not be at VHH any operation other than accel-

erated programming, or device damage may result. In

addition, the ACC pin must not be left floating or un-

connected; inconsistent behavior of the device may re-

sult.

Figure 3 illustrates the algorithm for the program oper-

ation. See the table, “Erase and Program Operations”

on page 57 in “AC Characteristics” for parameters,

and Figure 16 for timing diagrams.

AM29PDL128G Datasheet(PDF) 37 Page - Advanced Micro Devices

AM29PDL128G Datasheet(HTML) 37 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL