AM29BDS640G datasheet(7/77 Pages) AMD

7 / 77 page

May 9, 2006 25903C2

Am29BDS640G

Preliminary

Figure 22. Alternate Asynchronous Program Operation Timings 60

Figure 23. Synchronous Program Operation Timings .............. 61

Figure 24. Alternate Synchronous Program Operation Timings 62

Figure 25. Chip/Sector Erase Command Sequence................. 63

Figure 26. Accelerated Unlock Bypass Programming Timing .... 64

Figure 27. Data# Polling Timings (During Embedded Algorithm) 65

Figure 28. Toggle Bit Timings (During Embedded Algorithm)... 65

Figure 29. Synchronous Data Polling Timings/

Toggle Bit Timings ............................................................ 66

Figure 30. Latency with Boundary Crossing .......................... 67

Figure 31. Latency with Boundary Crossing

into Program/Erase Bank ................................................... 68

Figure 32. Example of Wait States Insertion (Standard

Handshaking Device) ........................................................ 69

Figure 33. Back-to-Back Read/Write Cycle Timings ............... 70

Erase and Programming Performance . . . . . . . . 71

FBGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 71

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 72

FBE080—80-ball Fine-Pitch Ball Grid Array (FBGA)

11 x 12 mm Package ...............................................................................72

AM29BDS640G Datasheet(PDF) 7 Page - Advanced Micro Devices