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AM42BDS640AGBC9IS Datasheet(PDF) 39 Page - Advanced Micro Devices |
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AM42BDS640AGBC9IS Datasheet(HTML) 39 Page - Advanced Micro Devices |
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39 / 72 page  38 Am42BDS640AG November 1, 2002 P R E L I M INARY TEST CONDITIONS Table 17. Test Specifications KEY TO SWITCHING WAVEFORMS CL Device Under Test Figure 8. Test Setup Test Condition All speed options Unit Output Load 1 TTL gate Output Load Capacitance, C L (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0.0–V IO V Input timing measurement reference levels V IO/2 V Output timing measurement reference levels V IO/2 V WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 9. Input Waveforms and Measurement Levels |
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