COM20022I3V-HT datasheet(3/83 Pages) SMSC

3 / 83 page

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM

Datasheet

SMSC COM20022I 3V

Page 3

Revision 02-27-06

DATASHEET

TABLE OF CONTENTS

Chapter 1

General Description .............................................................................................................6

Chapter 2

Pin Configuration................................................................................................................. 7

Chapter 3

Description of Pin Functions ............................................................................................... 8

Chapter 4

Protocol Description........................................................................................................... 11

4.1

Network Protocol ............................................................................................................................... 11

4.2

Data Rates......................................................................................................................................... 11

4.2.1

Selecting Clock Frequencies Above 2.5 Mbps .......................................................................................11

4.3

Network Reconfiguration ................................................................................................................... 12

4.4

Broadcast Messages......................................................................................................................... 13

4.5

Extended Timeout Function .............................................................................................................. 13

4.5.1

Response Time.......................................................................................................................................13

4.5.2

Idle Time.................................................................................................................................................13

4.5.3

Reconfiguration Time..............................................................................................................................13

4.6

Line Protocol ..................................................................................................................................... 13

4.6.1

Invitations To Transmit ...........................................................................................................................14

4.6.2

Free Buffer Enquiries..............................................................................................................................14

4.6.3

Data Packets ..........................................................................................................................................14

4.6.4

Acknowledgements.................................................................................................................................15

4.6.5

Negative Acknowledgements .................................................................................................................15

Chapter 5

System Description............................................................................................................. 16

5.1

Microcontroller Interface.................................................................................................................... 16

5.1.1

Selection of 8/16-Bit Access ...................................................................................................................19

5.1.2

DMA Transfers To And From Internal RAM ............................................................................................19

5.1.3

DMA Operation .......................................................................................................................................20

5.1.4

DMA Data Transfer Sequence (I/O to Memory: Read A Packet) ............................................................24

5.1.5

DMA Data Transfer Sequence (Memory to I/O: Write A Packet) ............................................................24

5.1.6

High Speed CPU Bus Timing Support ....................................................................................................24

5.2

Transmission Media Interface ........................................................................................................... 26

5.2.1

Traditional Hybrid Interface.....................................................................................................................26

5.2.2

Backplane Configuration.........................................................................................................................26

5.2.3

Differential Driver Configuration..............................................................................................................28

5.2.4

Programmable TXEN Polarity.................................................................................................................28

Chapter 6

Functional Description....................................................................................................... 30

6.1

Microsequencer................................................................................................................................. 30

6.2

Internal Registers .............................................................................................................................. 32

6.2.1

Interrupt Mask Register (IMR) ................................................................................................................32

6.2.2

Data Register..........................................................................................................................................32

6.2.3

Tentative ID Register ..............................................................................................................................32

6.2.4

Node ID Register ....................................................................................................................................33

6.2.5

Next ID Register .....................................................................................................................................33

6.2.6

Status Register .......................................................................................................................................33

6.2.7

Diagnostic Status Register .....................................................................................................................33

6.2.8

Command Register.................................................................................................................................34

6.2.9

Address Pointer Registers ......................................................................................................................34

6.2.10

Configuration Register ........................................................................................................................34

6.2.11

Sub-Address Register .........................................................................................................................34

6.2.12

Setup 1 Register .................................................................................................................................34

6.2.13

Setup 2 Register .................................................................................................................................34

6.2.14

Bus Control Register ...........................................................................................................................35

6.2.15

DMA Count Register ...........................................................................................................................36

6.3

Internal RAM ..................................................................................................................................... 46

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