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AM70PDL129CDH85IS Datasheet(PDF) 80 Page - Advanced Micro Devices |
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AM70PDL129CDH85IS Datasheet(HTML) 80 Page - Advanced Micro Devices |
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80 / 127 page  78 Am70PDL127CDH/Am70PDL129CDH November 24, 2003 ADV ANCE I N FO RMAT I O N TIMING DIAGRAMS Notes: Write Cycle 1. A write occurs during the overlap (t WP) of low CS#1s and low WE#. A write begins when CS#1s goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS#1s goes high and WE# goes high. The t WP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS#1s going low to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the end of write to the address change. tWR is applied in case a write ends with CS#1s or WE# going high. Notes: Deep Power Down Mode 1. When you toggle CS2s pin low, the device gets into the Deep Power Down mode after 0.5 ms suspend period. 2. To return to normal operation, the device needs Wake-up period. 3. Wake Up sequence is just the same as Power Up sequence. Figure 30. Timing Waveform of Write Cycle 3 Address Data Valid UB#, LB# WE# Data in Data out High-Z High-Z tWC tCW(2) tBW tWP(1) tDH tDW tWR(4) tAW tAS(3) CS#1s CS2s MODE Deep Power Down Mode Normal Operation 0.5 µs 200 µs Normal Operation Suspend Wake up CS#1s |
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