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AM70PDL129CDH85IS Datasheet(PDF) 122 Page - Advanced Micro Devices |
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AM70PDL129CDH85IS Datasheet(HTML) 122 Page - Advanced Micro Devices |
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122 / 127 page ![]() 120 Am70PDL127CDH/Am70PDL129CDH November 24, 2003 ADV ANCE I N FO RMAT I O N AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ V CC. Parameter Speed Options JEDEC Std. Description Unit t AVAV t WC Write Cycle Time (Note 1) Min 110 ns t AVWL t AS Address Setup Time Min 0 ns t ELAX t AH Address Hold Time Min 45 ns t DVEH t DS Data Setup Time Min 45 ns t EHDX t DH Data Hold Time Min 0 ns t GHEL t GHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns t WLEL t WS WE# Setup Time Min 0 ns t EHWH t WH WE# Hold Time Min 0 ns t ELEH t CP CE# Pulse Width Min 45 ns t EHEL t CPH CE# Pulse Width High Min 30 ns t WHWH1 t WHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 22 µs µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 17.6 µs µs Single Word/Byte Program Operation (Note 2, 5) Word Typ 100 µs Single Word/Byte Accelerated Programming Operation (Note 2, 5) Word Typ 90 µs t WHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec t RH RESET# High Time Before Write Min 50 ns |
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