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AM50DL128CH85IS Datasheet(PDF) 61 Page - SPANSION |
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AM50DL128CH85IS Datasheet(HTML) 61 Page - SPANSION |
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61 / 66 page ![]() February 6, 2004 Am50DL128CH 59 ADV ANCE I N FO RMAT I O N pSRAM DATA RETENTION Notes: 1. CE1#s ≥ V CC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled). 2. Typical values are not 100% tested. pSRAM POWER ON AND DEEP POWER DOWN Figure 32. Deep Power-down Timing Figure 33. Power-on Timing Parameter Symbol Parameter Description Test Setup Min Typ Max Unit V DR V CC for Data Retention CS1#s ≥ V CC – 0.2 V (Note 1) 2.7 3.3 V I DR Data Retention Current V CC = 3.0 V, CE1#s ≥ VCC – 0.2 V (Note 1) 1.0 (Note 2) 100 µA t CS CE2 Setup Time 0 ns t CH CE2 Hold Time 300 µs t DPD CE2 Pulse Width 10 ms t CHC CE2 Hold from CE#1 0 ns t CHP CE2 Hold from Power On 30 µs CE#1 CE#2 tDPD tCH tCS CE#1 VDD CE#2 tCHC tCHP tCH VDD min |
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