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Am29F010B

Am29F010B_00_C7 October 31, 2006

D A TA

SH EE T

AC CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

programming typicals assume checkerboard pattern.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4

for further information on command definitions.

6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles.

OE#

CE#

WE#

Data

Addresses

DQ7#

PA

Data# Polling

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Notes:

2. Figure indicates the last two bus cycles of the command sequence.

Figure 13.

Alternate CE# Controlled Write Operation Timings

Parameter

Limits

Comments

Typ (Note 1)

Max (Note 2)

Unit

Chip/Sector Erase Time

1.0

15

sec

Excludes 00h programming prior to

erasure (Note 4)

Byte Programming Time

7

300

µs

Excludes system-level overhead

(Note 5)

Chip Programming Time (Note 3)

0.9

6.25

sec