IR3084A datasheet(21/45 Pages) IRF

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IR3084A

Page 21 of 45

10/30/2006

Under Voltage Lockout (UVLO)

The UVLO function monitors the IR3084A’s VCC supply pin and ensures that there is adequate voltage to safely

power the internal circuitry. The IR3084A’s UVLO threshold is set higher than the minimum operating voltage of

compatible Phase ICs thus providing UVLO protection for them as well. UVLO at the Phase ICs is a function of

the Error Amplifier’s output voltage. When the IR3084A is in UVLO, the Error Amplifier is disabled and EAOUT is

at a very low voltage (<200mV) thus preventing the Phase ICs from becoming active.

During power-up, the IR3084A’s fault latch is reset when VCC exceeds 9.9V if there are no other faults. If the

VCC voltage drops below 9.1V the fault latch will be set.

Over Current Protection (OCP)

The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin

voltage, which is proportional to the average phase current plus DAC voltage, exceeds the OCSET voltage, the

over-current protection is triggered.

VID = Fault Code (NO_CPU)

When VIDSEL is grounded or left floating, NO_CPU VID codes of 11111XX for VR10 and 0000000X, 1111111X

for VR11 will set both the VID Fault Latch and the Fault Latch to disable the error amplifier. The controller will be

latched OFF and a power-on reset (POR) will be required to produce a new soft start sequence. In these 2

modes, the NO_CPU codes are ignored during startup. See Table 1 for further details.

When VIDSEL is set to VBIAS (6.9V) or VCC (12V), NO_CPU VID codes of 11111XX for VR10 and 0000000X,

1111111X for VR11 will set the Fault Latch to disable the error amplifier but the VID Fault Latch will not be set.

The controller will not be latched OFF and a soft start sequence will be produced when the NO_CPU code is

removed and the SS/DEL voltage falls below 0.215V. In these 2 modes, the NO_CPU codes will be not be

ignored during startup. See Table 1 for further details.

A 1.3µs delay is provided to prevent a NO_CPU fault condition from occurring during Dynamic VID changes.

VRRDY (Power Good) Output

The VRRDY pin is an open-collector output and should be pulled up to a voltage source through a resistor.

During soft-start, the VRRDY output remains low until the converter’s output voltage is in regulation and SS/DEL

is above 3.77V. The VRRDY pin transitions low if the fault latch is set. A high level at the VRRDY pin indicates

that the converter is in operation and has no fault, but does not ensure the output voltage is within the

specification. Output voltage regulation within the design limits can logically be assured however, assuming no

component failure in the system.

Load Current Indicator Output

The VDRP pin voltage represents the average phase current of the converter plus the DAC voltage. The load

current can be retrieved by subtracting the VDAC voltage from the VDRP voltage.

IR3084A Datasheet(PDF) 21 Page - International Rectifier