P80CL31HFP datasheet(17/68 Pages) PHILIPS

17 / 68 page

1997 Apr 15

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontrollers with

UART

P80CL31; P80CL51

11 TIMERS/EVENT COUNTERS

The P80CLx1 contains two16-bit timer/event counter

registers; Timer 0 and Timer 1, which can perform the

following functions:

• Measure time intervals and pulse durations

• Count events

• Generate interrupt requests.

In the ‘Timer’ operating mode the register is incremented

every machine cycle. Since a machine cycle consists of 12

oscillator periods, the count rate is 1

⁄12 × fosc.

In the ‘Counter’ operating mode, the register is

incremented in response to a HIGH-to-LOW transition.

Since it takes 2 machine cycles (24 oscillator periods) to

recognize a HIGH-to-LOW transition, the maximum count

rate is 1

⁄24 × fosc. To ensure a given level is sampled, it

should be held for at least one complete machine cycle.

Timer 0 and Timer 1 can be programmed independently to

operate in four modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32

prescaler.

Mode 1 16-bit time-interval or event counter.

Mode 2 8-bit time-interval or event counter with automatic

reload upon overflow.

Mode 3 Timer 0 establishes TL0 and TH0 as two

separate counters.

12 REDUCED POWER MODES

There are two software selectable modes of reduced

activity for further power reduction: Idle and Power-down.

12.1

Idle mode

Idle mode operation permits the external interrupts, UART,

and timer blocks to continue to function while the clock to

the CPU is halted.

Idle mode is entered by setting the IDL bit in the Power

Control Register (PCON.0, see Table 2). The instruction

that sets IDL is the last instruction executed in the normal

operating mode before the Idle mode is activated.

Once in Idle mode, the CPU status is preserved along with

the Stack Pointer, Program Counter, Program Status

Word and Accumulator. The RAM and all other registers

maintain their data during Idle mode. The status of the

external pins during Idle mode is shown in Table 3.

The following functions remain active during the Idle

mode:

• Timer 0 and Timer 1

• UART

• External interrupt.

These functions may generate an interrupt or reset; thus

ending the Idle mode.

There are two ways to terminate the Idle mode:

1. Activation of any enabled interrupt will cause IDL

(PCON.0) to be cleared by hardware thus terminating

the Idle mode. The interrupt is serviced, and following

the RETI instruction, the next instruction to be

executed will be the one following the instruction that

put the device in the Idle mode. The flag bits GF0

(PCON.2) and GF1 (PCON.3) may be used to

determine whether the interrupt was received during

normal execution or during the Idle mode.

For example, the instruction that writes to PCON.0 can

also set or clear one or both flag bits. When the Idle

mode is terminated by an interrupt, the service routine

can examine the status of the flag bits.

2. The second way of terminating the Idle mode is with an

external hardware reset. Since the oscillator is still

running, the hardware reset is required to be active for

two machine cycles (24 oscillator periods) to complete

the reset operation. Reset redefines all SFRs but does

not affect the on-chip RAM.

12.2

Power-down mode

Operation in Power-down mode freezes the oscillator.

The internal connections which link both Idle and

Power-down signals to the clock generation circuit are

shown in Fig.9.

Power-down mode is entered by setting the PD bit in the

Power Control Register (PCON.1, see Table 2).

The instruction that sets PD is the last executed prior to

going into the Power-down mode.

Once in the Power-down mode, the oscillator is stopped.

The contents of the on-chip RAM and the SFRs are

preserved. The port pins output the value held by their

respective SFRs. ALE and PSEN are held LOW.

In the Power-down mode, VDD may be reduced to

minimize circuit power consumption. The supply voltage

must not be reduced until the Power-down mode is

entered, and must be restored before the hardware reset

is applied which will free the oscillator. Reset should not be

released until the oscillator has restarted and stabilized.

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