ISL6549CBZ datasheet(12/18 Pages) INTERSIL

12 / 18 page

FN9168.2

September 22, 2006

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select

target crossover frequencies in the range of 10% to 30% of

the switching frequency, FSW.

Linear Controller Feedback Compensation

For most situations, no external compensation is required for

the linear output. As long as the output capacitor (COUT2) is

large (>100µF) and so is its ESR (>20mW), then it should be

stable for loads as low as 10mA up to at least 4A. If smaller

values of capacitance and/or ESR are desired, then special

considerations may be required to add external

compensation (as shown in Figure 8).

Component Selection Guidelines

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function of

the ripple current. The ripple voltage and current are

approximated by Equation 10.

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce the

converter’s response time to a load transient (and usually

increases the DCR of the inductor, which decreases the

efficiency). Increasing the switching frequency (FSW) for a

given inductor also reduces the ripple current and voltage.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6549 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval, the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

The response time to a transient is different for the application

of load and the removal of load. Equation 11 gives the

approximate response time interval for application and

removal of a transient load:

where: ITRAN is the transient load current step, tRISE is the

response time to the application of load, and tFALL is the

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the output

voltage setting. Be sure to check both of these equations at

the minimum and maximum output levels for the worst case

response time.

Output Capacitors Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current. The

load transient requirements are a function of the slew rate

(di/dt) and the magnitude of the transient load current. These

requirements are generally met with a mix of capacitors and

careful layout.

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. And keep in mind that not all

applications have the same requirements; some may need

many ceramic capacitors in parallel; others may need only one.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors.

The bulk capacitor’s ESR will determine the output ripple

voltage and the initial voltage drop after a high slew-rate

FP1

FZ2

OPEN LOOP E/A GAIN

FZ1

FP2

FLC

FCE

COMPENSATION GAIN

FREQUENCY

MODULATOR GAIN

FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP GAIN

dMAX V

⋅

VOSC

---------------------------------

log

--------

⎝⎠

⎛⎞

log

LOG

GMOD

GFB

GCL

∆VOUT = ∆I x ESR

∆I =

VIN - VOUT

FSW x L

--------------------------------

VOUT

VIN

----------------

•

(EQ. 10)

tFALL

LO ITRAN

VOUT

-------------------------------

tRISE

LO ITRAN

VIN VOUT

–

--------------------------------

(EQ. 11)

ISL6549

ISL6549CBZ Datasheet(PDF) 12 Page - Intersil Corporation

ISL6549CBZ Datasheet(HTML) 12 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL