PCD5002 datasheet(5/48 Pages) PHILIPS

5 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

PINNING

SYMBOL PIN

DESCRIPTION

ATL

alert LOW level output

ALC

alert control input

(normally LOW by internal pull-down)

DON

direct ON/OFF input

(normally LOW by internal pull-down)

REF

real time clock frequency reference

output

INT

interrupt output

n.c.

not connected

RST

reset input

(normally LOW by internal pull-down)

VPR

external positive voltage reference

input

SDA

I2C-bus serial data input/output

SCL

I2C-bus serial clock input

VDD

main positive supply voltage

VSS

main negative supply voltage

VPO

voltage converter positive output

CCP

voltage converter shunt capacitor

(positive side)

CCN

voltage converter shunt capacitor

(negative side)

TS1

test input 1

(normally LOW by internal pull-down)

XTAL2

decoder crystal oscillator output

XTAL1

decoder crystal oscillator input

n.c.

not connected

TS2

test input 2

(normally LOW by internal pull-down)

BAT

battery sense input

n.c.

not connected

RDI

received data input

(POCSAG or APOC-1)

RXE

receiver circuit enable output

ROE

receiver oscillator enable output

ZSD

synthesizer serial data output

ZSC

synthesizer serial clock output

ZLE

synthesizer latch enable output

VSS

main negative supply voltage

VIB

vibrator motor drive output

LED

LED drive output

ATH

alert HIGH level output

Fig.2 Pin configuration for SOT358-1 (LQFP32).

ATL

ALC

DON

REF

INT

n.c.

RST

RXE

RDI

n.c.

BAT

TS2

n.c.

XTAL1

XTAL2

PCD5002H

MGD080

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