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PCD8544 Datasheet(PDF) 23 Page - NXP Semiconductors |
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PCD8544 Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 32 page ![]() 1999 Apr 12 23 Philips Semiconductors Product specification 48 × 84 pixels matrix LCD controller/driver PCD8544 The pinning is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 48 × 84 pixels. 11 100000100 data write 12 100011111 data write 13 000001101 display control; set inverse video mode (D=1andE=1) 14 010000000 set X address of RAM; set address to ‘0000000’ 15 100000000 data write STEP SERIAL BUS BYTE DISPLAY OPERATION D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGL677 MGL678 MGL679 MGL679 MGL680 Fig.17 Application diagram. handbook, halfpage MGL635 DISPLAY 48 × 84 pixels PCD8544 I/O VDD VSS VLCD Cext 8 84 24 24 The required minimum value for the external capacitors is: Cext = 1.0 µF. Higher capacitor values are recommended for ripple reduction. 14 BONDING PAD LOCATIONS 14.1 Bonding pad information (see Fig.18) PARAMETER SIZE Pad pitch min. 100 µm Pad size, aluminium 80 × 100 µm Bump dimensions 59 × 89 × 17.5 (±5) µm Wafer thickness max. 380 µm |
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