SC16C652BIB48 datasheet(21/43 Pages) NXP

21 / 43 page

NXP Semiconductors

SC16C652B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/

decoder

Bit

Symbol

Description

logic 1 = divide-by-4 clock input

MCR[6]

IR enable (see Figure 17).

logic 0 = enable the standard modem receive and transmit input/output interface (normal

default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the

TX/RX output/inputs are routed to the infrared encoder/decoder. The data input and output

levels will conform to the IrDA infrared interface requirement. As such, while in this mode,

the infrared TX output will be a logic 0 during idle data conditions.

MCR[5]

Reserved; set to ‘0’.

MCR[4]

Loopback. Enable the local Loopback mode (diagnostics). In this mode the transmitter output

(TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C652

B I/O pins. Internally the modem data and control pins are connected into a loopback data

configuration (see Figure 5). In this mode, the receiver and transmitter interrupts remain fully

operational. The Modem Control Interrupts are also operational, but the interrupts’ sources are

switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the

IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

MCR[3]

OP2/INT enable

logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2 to a logic 1 (normal

default condition)

logic 1 = forces the INT (A, B) outputs to the active mode and sets OP2 to a logic 0

MCR[2]

(OP1). OP1A/OP1B are not available as an external signal in the SC16C652B. This bit is

instead used in the Loopback mode only. In the Loopback mode, this bit is used to write the

state of the modem RI interface signal.

MCR[1]

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

MCR[0]

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

Table 20. Modem Control Register bits description...continued

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C652B and the CPU.

Bit

Symbol

Description

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the current FIFO data.

This bit is cleared when there are no remaining error flags associated with the remaining data in

the FIFO.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the

transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever

either the THR or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’ whenever the

transmit FIFO and transmit shift register are both empty.

Table 21. Line Status Register bits description

SC16C652B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.0 — 2 November 2023

21 / 43

SC16C652BIB48 Datasheet(PDF) 21 Page - NXP Semiconductors

SC16C652BIB48 Datasheet(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL