AMSN2800DUT4C datasheet(13/102 Pages) AMD

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Chapter 1

Overview

26426C—October 2003

AMD Athlon™ MP Processor Model 10 Data Sheet for Multiprocessor Platforms

Preliminary Information

1Overview

The AM D Athlon™ M P processor model 10 powers the next

generation in computing platforms, delivering compelling

performance for cutting-edge applications and an unprecedented

computing experience.

The AMD Athlon™ MP processor model 10, based on leading-

edge 0.13 micron technology and increased on-chip cache,

integrates the innovative design and manufacturing expertise of

AMD to deliver improved performance, while maintaining the

stab le and compatible Socket A in frastruc tu re o f th e

AMD Athlon MP processor. The AMD Athlon MP processor

model 10 continues to deliver breakthrough performance in the

multiprocessing server and workstation markets. This processor

is designed to meet the reliability and computation-intensive

requirements of cutting-edge software applications required by

workstations and servers.

Delivered in an OPGA package, the AMD Athlon MP processor

model 10 delivers the integer, floating-point, and 3D multimedia

performance for enterprise applications running on x86 system

platforms. The AMD Athlon MP processor model 10 offers

compelling performance for productivity software, including

workstation-class digital content creation (DCC), electronic

design automation (EDA), and computer-aided design (CAD), as

well as infrastructure and collaborative server applications. It

also offers the scalability and reliability that IT managers and

business users require for mission-critical computing.

The AMD Athlon MP processor model 10 features the seventh-

generation microarchitecture, including a high-speed execution

core that includes multiple x86 instruction decoders, a dual-

ported, 128-Kbyte, split level-one (L1) cache, a 512-Kbyte on-

chip L2 cache, three independent integer pipelines, three

address calculation pipelines, and a superscalar, fully pipelined,

out-of-order, three-way floating-point engine. The integrated L2

cache supports the growing processor and system bandwidth

requirements of emerging software, graphics, I/O, and memory

technologies. The processor also features the advanced modified

owner exclusive shared invalid (MOESI) cache coherency

protocol to ensure efficient cache integrity in a multiprocessing

environment. The floating-point engine is capable of delivering

excellent performance on the numerically complex applications

typical of servers and workstations.

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