PCF8578USLASH2 datasheet(15/44 Pages) PHILIPS

15 / 44 page

1998 Sep 08

Philips Semiconductors

Product speciﬁcation

LCD row/column driver for dot matrix

graphic displays

PCF8578

7.9

Display mode controller

The configuration of the outputs (row or column) and the

selection of the appropriate driver waveforms are

controlled by the display mode controller.

7.10

Display RAM

The PCF8578 contains a 32 x 40-bit static RAM which

stores the display data. The RAM is divided into 4 banks

of 40 bytes (4 x 8 x 40 bits). During RAM access, data is

transferred to/from the RAM via the I2C-bus. The first

eight columns of data (0 to 7) cannot be displayed but

are available for general data storage and provide

compatibility with the PCF8579. There is a direct

correspondence between X-address and column output

number.

7.11

Data pointer

The addressing mechanism for the display RAM is

realized using the data pointer. This allows an individual

data byte or a series of data bytes to be written into, or read

from, the display RAM, controlled by commands sent on

the I2C-bus.

7.12

Subaddress counter

The storage and retrieval of display data is dependent on

the content of the subaddress counter. Storage takes

place only when the contents of the subaddress counter

agree with the hardware subaddress. The hardware

subaddress of the PCF8578, valid in mixed mode only, is

fixed at 0000.

7.13

I2C-bus controller

The I2C-bus controller detects the I2C-bus protocol, slave

address, commands and display data bytes. It performs

the conversion of the data input (serial-to-parallel) and the

data output (parallel-to-serial). The PCF8578 acts as an

I2C-bus slave transmitter/receiver in mixed mode, and as

a slave receiver in row mode. A slave device cannot

control bus communication.

7.14

Input ﬁlters

To enhance noise immunity in electrically adverse

environments, RC low-pass filters are provided on the

SDA and SCL lines.

7.15

RAM access

RAM operations are only possible when the PCF8578 is

in mixed mode.

In this event its hardware subaddress is internally fixed at

0000 and the hardware subaddresses of any PCF8579

used in conjunction with the PCF8578 must start at 0001.

There are three RAM ACCESS modes:

• Character

• Half-graphic

• Full-graphic.

These modes are specified by bits G1 to G0 of the RAM

ACCESS command. The RAM ACCESS command

controls the order in which data is written to or read from

the RAM (see Fig.10).

To store RAM data, the user specifies the location into

which the first byte will be loaded (see Fig.11):

• Device subaddress (specified by the DEVICE SELECT

command)

• RAM X-address (specified by the LOAD X-ADDRESS

command)

• RAM bank (specified by bits Y1 and Y0 of the RAM

ACCESS command).

Subsequent data bytes will be written or read according to

the chosen RAM ACCESS mode. Device subaddresses

are automatically incremented between devices until the

last device is reached. If the last device has

subaddress 15, further display data transfers will lead to a

wrap-around of the subaddress to 0.

7.16

Display control

The display is generated by continuously shifting rows of

RAM data to the dot matrix LCD via the column outputs.

The number of rows scanned depends on the multiplex

rate set by bits M1 and M0 of the SET MODE command.

The display status (all dots on/off and normal/inverse

video) is set by bits E1 and E0 of the SET MODE

command. For bank switching, the RAM bank

corresponding to the top of the display is set by bits

B1 and B0 of the SET START BANK command. This is

shown in Fig.12. This feature is useful when scrolling in

alphanumeric applications.

7.17

TEST pin

The TEST pin must be connected to VSS.

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