NXP Semiconductors

MF4SAM3X_ SDS

MIFARE SAM AV3 secure access module

9 Dynamic characteristics

Remark: The P6022y VB only supports one single IO1.

9.1 General, ISO/IEC 7816 I/O and ISO/IEC 14443 I/O interfaces

Conditions: VDD = 1.62 V to 5.5 V; VSS = 0 V; Tamb = -25°C to 85 °C, unless otherwise specified

Symbol Parameter

Conditions

Min Typ[1] Max

Unit

Input/Output: IO1, IO2 and IO3

-

-

1

μs

tr(i)

Input rise time

Input/reception mode

[2]

[3]

-

-

0.25 ×

tIOWx_min

μs

s

-

-

1

μs

tf(i)

Input fall time

Input/reception mode

[2]

[3]

-

-

0.25 ×

tIOWx_min

μs

tr(o)

Output rise time

Output/transmission mode; CL = 30 pF

-

-

0.1

μs

tf(o)

Output fall time

Output/transmission mode; CL = 30 pF

-

-

0.1

μs

Inputs: CLK and RST_N

fCLK

External clock frequency

in ISO/IEC 7816 UART

applications

tCLKW, Tamb and VDD in their spec'd limits

[4] 0.85 -

11.5

MHz

tCLKW

Clock pulse width i.r.t. clock

period (positive pulse duty

cycle of CLK)

[5] 40

-

60

%

tr(i)CLK

CLK input rise time

[6] -

-

see [6]

tf(i)CLK

CLK input fall time

[6] -

-

see [6]

tr(i)RST

RST_N input rise time

[7] -

-

400

μs

tf(i)RST

RST_N input fall time

[7] -

-

400

μs

tRW

Reset pulse width (RST_N

low)

40

-

-

μs

tWKP

Wake-up time from SLEEP

mode

fCLKmin ≤ fCLK ≤ fCLKmax

-

17

20

μs

level triggered ext.int.

-

20

-

μs

tWKPIO

I/Ox LOW time for wake-up

from SLEEP mode

edge triggered ext.int.

-

20

-

μs

tWKPRST RST_N LOW time for wake-up

from SLEEP mode

40

-

-

μs

Inputs: CLK, RST_N, IO1, IO2, IO3

CPIN

Pin capacitances CLK,

RST_N, IO1, IO2, IO3

Test frequency = 1 MHz; Tamb = 25 °C

-

-

10

pF

Table 10. Electrical AC characteristics of IO1, IO2, IO3, CLK and RST_N

[1]

Typical values are only referenced for information. They are subject to change without notice.

[2]

At minimum IOx input signal HIGH or LOW level voltage pulse width of 3.2 µs. This timing specification applies to ISO7816 configurations down to a

minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1 = 0x96, (Fi/Di) = (512/32)), for example.

[3]

At minimum IOx input signal HIGH or LOW level voltage pulse width of less than 3.2 µs. This timing specification applies to ISO7816 configurations

beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/

MF4SAM3X_SDS

All information provided in this document is subject to legal disclaimers.

© 2024 NXP B.V. All rights reserved.

Product short data sheet

Rev. 3.2 — 5 March 2024

16 / 26