3D3521 datasheet(2/4 Pages) DATADELAY

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3D3521

APPLICATION NOTES

The 3D3521 Manchester Encoder samples the

data input at the rising edge of the input clock.

The sampled data is used in conjunction with the

clock rising and falling edges to generate the by-

phase level Manchester code.

INPUT SIGNAL CHARACTERISTICS

The 3D3521 Manchester Encoder inputs are

CMOS compatible. The user should assure

himself that the 50% (of VDD) threshold is used

when referring to all timing, especially to the input

clock duty cycle.

CLOCK DUTY CYCLE ERRORS

The 3D3521 Manchester Encoder employs the

timing of the clock rising and falling edges (duty

cycle) to implement the required coding scheme.

To reduce the difference between the output data

high time and low time, it is essential that the

deviation of the input clock duty cycle from 50/50

be minimized.

OUTPUT SIGNAL CHARACTERISTICS

The 3D3521 presents at its outputs the true and

the complimented encoded data.

The High-to-Low time skew of the selected data

output should be budgeted by the user, as it

relates to his application, to satisfactorily

estimate the distortion of the transmitted data

stream.

Such an estimate is very useful in determining

the

functionality and margins of the data link, if a

3D3522 Manchester Decoder is used to decode

the received data.

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

CMOS integrated circuitry is strongly dependent

on power supply and temperature. The

monolithic 3D3521 Manchester encoder utilizes

novel and innovative compensation circuitry to

minimize timing variations induced by fluctuations

in power supply and/or temperature.

RESET

(RESB)

CLOCK

(CIN)

DATA

(DIN)

TRANSMIT

(TX)

TRANSMIT

(TXB)

tDS

tDH

Figure 1: Timing Diagram

1/fC

10110010

Power-on reset (Left high for normal operation)

T2H

T2L

T1H

T1L

Doc #06004

DATA DELAY DEVICES, INC.

5/8/2006

Tel: 973-773-2299

Fax: 973-773-9672

http://www.datadelay.com

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