DSP56362P datasheet(80/152 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56362 Technical Data, Rev. 4

3-54

Freescale Semiconductor

Figure 3-34 SPI Master Timing (CPHA = 0)

159

SS deassertion to HREQ output not

deasserted (CPHA = 0)

Slave

—

2.5

×T

C+30

—

160

SS deassertion pulse width (CPHA = 0)

Slave

—

TC+6

—

161

HREQ in assertion to first SCK edge

Master

Bypassed

Narrow

Wide

0.5

× t

SPICC +

2.5

×T

C+43

0.5

×t

SPICC +

2.5

×T

C+43

0.5

×t

SPICC +

2.5

×T

C+43

121

174

209

—

162

HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

—

163

First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

—

Note: Periodically sampled, not 100% tested

Table 3-21 Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics

Mode

Filter Mode

Expression

100MHz

Unit

Min

Max

(Input)

MISO

(Input)

Valid

MOSI

(Output)

MSB

Valid

LSB

MSB

LSB

HREQ

(Input)

141

142

143

144

141

144

143

142

148

149

148

152

153

163

161

AA0271

SCK (CPOL=0

(Output)

SCK (CPOL = 1

(Output)

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