DSP56366 datasheet(70/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

3-44

Freescale Semiconductor

143

Serial clock low period

Master

Bypassed

0.5

×t

SPICC –10

—

Narrow

0.5

×t

SPICC –10

—

Wide

0.5

×t

SPICC –10

126.5

—

Slave

Bypassed

2.5

×T

C+12

32.8

—

Narrow

2.5

×T

C+102

122.8

—

Wide

2.5

×T

C+189

209.8

—

144

Serial clock rise/fall time

Master

—

Slave

—

2000

146

SS assertion to first SCK edge

CPHA = 0

Slave

Bypassed

3.5

×T

C+15

44.2

—

Narrow

—

Wide

—

CPHA = 1

Slave

Bypassed

—

Narrow

—

Wide

—

147

Last SCK edge to SS not asserted

Slave

Bypassed

—

Narrow

102

—

Wide

189

—

148

Data input valid to SCK edge (data input

set-up time)

Master/Slave

Bypassed

—

Narrow

MAX{(20-TC), 0}

11.7

—

Wide

MAX{(40-TC), 0}

31.7

—

149

SCK last sampling edge to data input not

valid

Master/Slave

Bypassed

2.5

×T

C+10

30.8

—

Narrow

2.5

×T

C+30

50.8

—

Wide

2.5

×T

C+50

70.8

—

150

SS assertion to data out active

Slave

—

151

SS deassertion to data high impedance2

Slave

—

Table 3-19 Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics1

Mode

Filter

Mode

Expression

Min

Max

Unit

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