DSP56371 datasheet(39/68 Pages) FREESCALE

39 / 68 page

Reset, Stop, Mode Select, and Interrupt Timing

DSP56371 Data Sheet, Rev. 4.1

Freescale Semiconductor

Delay from interrupt trigger to interrupt code

execution.

10 xTC + 5

60.0

Duration of level sensitive IRQA assertion to

ensure interrupt service (when exiting Stop)2, 3

• PLL is active during Stop and Stop delay is

enabled

(OMR Bit 6 = 0)

9+(128K

× TC)

704

—

• PLL is active during Stop and Stop delay is not

enabled

(OMR Bit 6 = 1)

× TC

138

—

• PLL is not active during Stop and Stop delay is

enabled (OMR Bit 6 = 0)

9+(128KxTC)+Tlock

5.7

• PLL is not active during Stop and Stop delay is

not enabled (OMR Bit 6 = 1)

(25 x TC)+Tlock

5ms

• Delay from IRQA, IRQB, IRQC, IRQD, NMI

assertion to general-purpose transfer output

valid caused by first interrupt instruction

execution

10 x TC + 3.0

59.0

Interrupt Requests Rate

• ESAI, ESAI_1, SHI, DAX, Timer

12 x TC

——

•DMA

8 x TC

——

•IRQ, NMI (edge trigger)

8 x TC

——

•IRQ (level trigger)

12 c TC

——

DMA Requests Rate

• Data read from ESAI, ESAI_1, SHI, DAX

6 x TC

——

• Data write to ESAI, ESAI_1, SHI, DAX

7 x TC

——

•Timer

2 x TC

——

•IRQ, NMI (edge trigger)

3 x TC

——

Note:

1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply

to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is

recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

2. For PLL disable, using external clock (PCTL Bit 13 = 0), no stabilization delay is required and recovery time will be

defined by the OMR Bit 6 settings.

For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the

PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms.

3. Periodically sampled and not 100% tested

4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and

valid. When the VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet

met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up.

Designs should minimize this state to the shortest possible duration.

Table 19. Reset, Stop, Mode Select, and Interrupt Timing (continued)

No.

Characteristics

Expression

Min

Max

Unit

DSP56371 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

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