EM65567AF datasheet(21/93 Pages) EMC

21 / 93 page

Preliminary

EM65567

66 COM/ 96 SEG 256 Color STN LCD Driver

* This specification is subject to be changed without notice.

2003/1/9 (V0.1)

The EM65567 can be read the control registers, in case of control register read operation, data bus upper nibble (D3-D0) use

for register address (0 to FH). In maximum, 16 registers can access directly. But number of register is more than 16 registers.

Therefore, EM65567 has register bank control. The RE register is set bank number to access. And the RE address is 0FH, in

any bank can access RE register. It is need 4-steps to read the specific register in maximum case.

(1) Write 04H to RE register for access to RA register.

(2) Writes specific register address to RA register.

(3) Write specific register bank to RE register.

(4) Read specific register contents.

D0~D7

bank

data

addr

04H

RDB

WRB

Bank number write

to RE for RA

Address write

to RA

Bank number

write to RE

read specific

Figure 8. Register read operation

7.4 16-bit Data Access to Display RAM

The EM65567 correspond to 8-bits and 16-bits bus size access.

The data bus size can select by WLS register.

WLS = “0”: 8-bits bus size

WLS = “1”: 16-bits bus size

In the 16-bits access mode, access for control register use low-byte data bus (D7~D0). Then high byte data bus (D15~D8) are

not used in internal circuit. When read control register using 16-bits bus. Register values output to D3-D0 and D15-D4 output

“H”. 16-bit access is only effective for access to the display RAM.

7.5 Display Start Address Register

This register determines the Y-address of the display RAM corresponding to the display start line. The display RAM data that

addressed Display Start Address register output to common driver start line. The actual common start line of LCD panel

depend on Display Start Common register and SHIFT bit of Display Control register. The register are preset every timing of

FLM signal variation in the display line counter. The line counter counts up being synchronized with LP input and generates

line addresses which read out sequentially 288 bits data from display RAM to LCD drive circuit.

7.6 Addressing of Display RAM

The EM65567 has built-in bit mapped display RAM. The display RAM consists of 768 bits (8 bits*96) in the X-direction and

66 bits in the Y-direction. In the gradation display mode, the EM65567 provides segment driver output for 8-gradation

display using 3 bits and that for 4-gradation display using 2 bits. The three outputs of the segment driver can be used for one

pixel of RGB. When connected to an STN color LCD panel, the EM65567 can display 96*66 pixels with 256 colors (8

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