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MBM29SL800TD-10 Datasheet(PDF) 21 Page - SPANSION

Part # MBM29SL800TD-10
Description  FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
PDF  56 Pages
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MBM29SL800TD-10 Datasheet(HTML) 21 Page - SPANSION

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MBM29SL800TD-10/12/MBM29SL800BD-10/12
21
See “Hardware Sequence Flags Table”.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows :
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags Table” and “(15) DQ2 vs. DQ6” in sTIMING
DIAGRAM.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7 to DQ0 on the following read cycle.
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, deter-
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the begining of the algorithm when it returns to determine the status
of the operation. (Refer to “Toggle Bit Algorithm” in “sFLOW CHART”.)
Toggle Bit Status
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Toggle*1
Erase-Suspend Read
(Erase-Suspended Sector)
11
Toggle
Erase-Suspend Program
DQ7
Toggle
1*2



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