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33389 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc

Part # 33389
Description  System Basis Chip with Low Speed Fault Tolerant CAN
PDF  49 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33389 Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33389
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V
≤ V
SUP ≤ 18 V, - 40°C ≤ T
A ≤ 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
MICROCONTROLLER INTERFACE
AC CANL/CANH Slew Rates, Rising or Falling Edges, TX from Recessive to
Dominant State
CLOAD - 10 nF, 133 Ω Termination Resistors
tCANRD
3.5
5.0
10
V/µs
AC CANL/CANH Slew Rates, Rising or Falling Edges, TX from Dominant to
Recessive State
CLOAD - 10 nF, 133 Ω Termination Resistors
tCANDR
2.0
3.5
10
V/µs
AC Propagation Delay TX to RX Low
CLOAD - 10 nF, 133 Ω Termination Resistors
tDH
—
1.2
2.0
µs
AC Propagation Delay TX to RX High
CLOAD - 10 nF, 133 Ω Termination Resistors
tDL
—
2.0
3.0
µs
Wake-Up Filter Time
tWUFT
8.0
20
38
µs
RST Duration after V1 High
tRES
—
1.0
—
ms
SCLK Clock Period
tPSCLK
500
—
—
ns
SCLK Clock High Time
tWSCLKH
175
—
—
ns
SCLK Clock Low Time
tWSCLKL
175
—
—
ns
Falling Edge of CS to Rising Edge of SCLK
tLEAD
250
50
—
ns
Falling Edge of SCLK to Rising Edge of CS
tLEAD
250
50
—
ns
SI to Falling Edge of SCLK
tSISU
125
25
—
ns
Falling Edge of SCLK to SI
tSI(HOLD)
125
25
—
ns
SO Rise Time (CL = 200 pF)
tRSO
—
25
75
ns
SO Fall Time (CL = 200 pF)
tFSO
—
25
75
ns
SI, CS, SCLK Incoming Signal Rise Time
tRSI
—
—
200
ns
SI, CS, SCLK Incoming Signal Fall Time
tFSI
—
—
200
—
Time from Falling Edge of CS to SO
Low Impedance
High Impedance
tSO(EN)
tSO(DIS)
—
—
200
200
ns
Time from Rising Edge of SCLK to SO Data Valid
0.2 V1 or V2 < SO > 0.8 V1 or V2, CL = 200 pF
tVALID
—
50
125
—
Running Mode Oscillator Tolerance (Normal Request, Normal and Stand-by
Modes (9))
RMOT
-12
—
+12
%
Software Watchdog Timing 1 (9)
tSW1
4.4
5.0
5.6
ms
Software Watchdog Timing 2 (9)
tSW2
8.8
10
11.2
ms
Software Watchdog Timing 3 (9)
tSW3
17.6
20
22.4
ms
Software Watchdog Timing 4 (9)
tSW4
28
32
36
ms
Notes
9.
Software watchdog timing accuracy is based on the running mode oscillator tolerance



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